CPU simulator

A CPU simulator shows what a processor does, one step at a time, as it runs a program. Our CPU Simulator runs a small assembly language based on Little Man Computer and AQA mnemonics, and steps through the fetch-decode-execute cycle in register transfer notation, lighting up the program counter, MAR, MDR, CIR, accumulator and the buses as each one is used.

It opens on a short program that adds two numbers held in memory, 25 and 17, and outputs 42.

Try it

CPU Simulator

Step through fetch, decode and execute in assembly

Open the simulatorGo to its page

How to use the CPU simulator

1. Under Program, type an assembly program, or choose one from Examples: add two numbers, count down, the larger of two inputs, multiplication, a sum from 1 to n, Fibonacci numbers, masks and shifts, or running into data.
2. If the program uses INP, type its inputs in Inputs, for INP.
3. Errors are reported against each line, such as a missing label or a value out of range.
4. Under Run, step forwards and backwards through the run, one register transfer at a time.
5. Watch the registers, the memory grid and the address, data and control buses light up, and read the note under each step. Show memory in decimal or hex.

The Instructions panel lists every mnemonic. Write #5 for the number 5, or a label or address for what is in memory there; labels end in a colon and comments start with a semicolon.

The instruction set

Memory has 64 addresses, and each holds a whole number from −32,768 to 32,767. An instruction is one word: the opcode times 256 plus the operand, so LDA 5 is stored as 1 × 256 + 5 = 261.

The fetch-decode-execute cycle

Step through the first instruction of the opening program, LDA first, and the simulator shows each register transfer:

Square brackets mean "the contents of". The whole five-instruction program takes 37 steps, including the start, and outputs 25 + 17 = 42.

Check yourself:

Example programs to try

Count down

A loop that outputs 5, 4, 3, 2, 1, 0: it outputs the accumulator, uses BRZ to stop once it reaches zero, subtracts 1 with SUB #1, and uses BRA to jump back. Watch the branch change the program counter, so execution jumps back instead of moving on.

Running into data

A program with no HLT runs on into its data, and the CPU tries to execute a number as an instruction. This is why every program needs a HLT before its DAT lines; if the program counter runs past the last address, the simulator stops with a fault and asks whether a HLT was missed.

What the simulator does not do

• One accumulator. There are no general-purpose registers R0 to R12, so programs written for the full AQA instruction set with registers need rewriting.
• No stack, interrupts or subroutines. The machine has branches only.
• No pipelining or cache. It runs one instruction at a time, to show the cycle clearly.

Common mistakes

• Mixing up the MAR and the MDR. The MAR holds an address; the MDR holds the data read from or written to it. AQA calls the MDR the memory buffer register (MBR).
• Forgetting the PC increments during fetch. It already points to the next instruction while the current one executes.
• Confusing #5 with 5. #5 is the number 5; plain 5 means the contents of address 5.
• Leaving out HLT. Without it, the CPU runs on into the data.

Practise computer systems in a short timed paper

The CPU and the fetch-decode-execute cycle come up in GCSE Computer Science and A-level Computer Science practice. Each daily paper is a short timed paper of 8 questions worth 25 to 35 marks, and the papers mix topics. Our how does a CPU work guide explains the parts of the processor, and the PC Components course covers cores and clock speed.

Read next

Computer Science · Computer systemsHow does a CPU work? Fetch, decode, execute explainedHow a CPU works, step by step: the fetch, decode, execute cycle, the registers it uses, and why clock speed, cores and cache make it faster.